General information - physics lab course nano electronic for Master

• Within the first two weeks of the lecture period in SS (time to be announced), an introduction to the organization of the lab-courses for block A, C and D will be given.
• The lab course starts 11.03.2024 and will end with the lecture period of the summer term. Dates during lecture time in block A are typically on Wednesday. The scheduling of dates in block C is done by arrangement. (see further information).
• All experiments are done in groups of two to three students (register via RWTH online). After registration your group can choose the preferred experimental block in the moodle room of the lab-course.
• The experiment report for experiments N1 to N7 (block A) have to be handed via email within two weeks after the experiment. Where to hand in the Jülich experiments (J-experiments) has to be confirmed with the respective tutor of the experiment. Only in exceptional cases and prior agreement with the tutor and extension of the two week deadline is possible.
• The experiments start at 9:00h.
• All participants complete seven days of experiments from block A, B, C and D.
  
• Block A:
  The experiments in this block are N1 to N7. The experiments are carried out in the rooms of the lab course in Modulbau Physik or at the IHT.
• Block B:
  Experiments will take place in Jülich. In the time period 11.03.2024 - 18.03.2024 (no experiments on weekends) you will attend a full day lecture on 11.03.2024 and conduct 2-4 experiments in the following five days.
  The lecture will give you an introduction for the experiments and a general overview of research topics in nano electronic in the Forschungszentrum Jülich.
  The experiments will be assigned at the end of February. Instructions can be found here: http://www.fz-juelich.de/pgi/lcn/
  The lecture talks on Monday (11.03.2024 9:00) take place in Building 02.4w E1. room Nr. 309b. If possible, for 11.03.2024 a bus will be organized picking you up in Aachen and bringing you to Jülich directly. Information on this service will be provided via email to registered participants in time. On the other days, the bus line SB20 can be used to reach the Research Center.
  For entering the Forschungszentrum you need your ID card or a passport.
  Directions to the Forschungszentrum can be found here: http://www.fz-juelich.de/portal/EN/Service/Howtoreachus/_node.html
  The meeting point for the experiments on Tuesday - Friday is at 9:00h in Building 02.4w E1 room 309b. The room is on the first floor.
  
• Block C: (maximum of six students, i.e. two groups):
  The experiment block "from material to a device" covers five days and gives you a practical introduction for important aspects of electronic ceramics for future memory technologies. The remaining experimental days will be covered by experiments of Block B. Exemplary a ferromagnetic RAM memory cell will be assembled and characterised and compared with a DRAM. All technological steps for the preparation of electro ceramic thin films will be introduced and carried out. Afterwards, the for memory cells relevant properties are measured. The individual steps include:
  
• Wet chemical deposition and technology of ceramic thin films part I: preparation of wet chemical plating solutions in a chemical lab.
• Wet chemical deposition and technology of ceramic thin films part II: deposition of the afore prepared solutions for the fabrication of ferroelectric capacities.
• Integration of the ferroelectric capacitors on a chip carrier and contacting using wedge-wedge-bonding.
• Electrical characterisation of the encapsulated electro ceramic thin films.
• Assembly and computer controlled accessing of a 2x2 memory array consisting of 1T/1C FeRAM cells.
The experiments take place at the Institut für Werkstoffe der Elektrotechnik II. Contact: Dr. Theodor Schneller
• Block D: (maximum of seven students, i.e. two/three groups):
  The experiment block "CMOS Lab course" covers seven days and takes place every second Wednesday during the lecture period. Objectives of the course are
  • Fabrication of a Si-chip with CMOS transistors and digital circuit building blocks (inverters, NAND-gate, half-adder)
  • Characterization of the fabricated transistors allows observing the impact of fabrication on device and circuit performance
  During the course you will learn how to do cleanroom fabrication including
  • wafer cleaning, optical lithography, plasma-enhanced CVD, rapid thermal oxidation, dry etching (ICP-RIE), metalization (etching and lift-off)
  Device characterization includes:
  • spectroscopic ellipsometry, scanning electron microscopy, electrical transport
    
  The experiments take place at the Insitut für Halbleitertechnik (IHT). Contact: Dr. Birger Berghoff

• Cheating or fraud, e.g. tuning data or copying text (even partial) for reports, will result in the immediate disqualification of the lab course without advance warning.