Experiments and Instructions

Every group completes seven days of experiments ("Versuchstage" VT):

Experimental block A:

• Single day experiments (N2, N4, N6, N7):
  These will take place on Wednesday during term time.
• Two-day experiments (N1):
  The first day will be a Wednesday during term time; the second day will take place within one week (latest on the following Tuesday), in accordance with the tutor.

Depending on the number of participants, some dates might be during the semester break.

Experimental block B:

• 4 lab days: 2-4 experiments from Laboratory experiments in Jülich.
  The experiments take place as part of the JARA-FIT Ferienpraktikums "Nanoelektronik" in the week 10.03.2025 - 17.03.2025 in Jülich (no additional registration on the Jülich webpage required). All participants have to take part in the full-day introduction lecture on 10.03.2025.

Experimental block C:

• 5 lab days: Experimental block "from material to a device" (Institut für Werkstoffe der Elektrotechnik)
• The experiments take place during the term SS 2025. The dates are arranged with the respective tutor.
The experiment block "from material to a device" covers five days and gives you a practical introduction for important aspects of electronic ceramics for future memory technologies. Exemplary a ferromagnetic RAM memory cell will be assembled and characterised and compared with a DRAM. All technological steps for the preparation of electro ceramic thin films will be introduced and carried out. Afterwards, the for memory cells relevant properties are measured. The individual steps include:

• Wet chemical deposition and technology of ceramic thin films part I: preparation of wet chemical plating solutions in a chemical lab.
• Wet chemical deposition and technology of ceramic thin films part II: deposition of the afore prepared solutions for the fabrication of ferroelectric capacities.
• Integration of the ferroelectric capacitors on a chip carrier and contacting using wedge-wedge-bonding.
• Electrical characterisation of the encapsulated electro ceramic thin films.
• Assembly and computer controlled accessing of a 2x2 memory array consisting of 1T/1C FeRAM cells.

Experimental block D:

7 lab days: The experiment block "CMOS Lab course" covers seven days and takes place every second Wednesday during the lecture period. Objectives of the course are

• Fabrication of a Si-chip with CMOS transistors and digital circuit building blocks (inverters, NAND-gate, half-adder)
• Characterization of the fabricated transistors allows observing the impact of fabrication on device and circuit performance
• wafer cleaning, optical lithography, plasma-enhanced CVD, rapid thermal oxidation, dry etching (ICP-RIE), metalization (etching and lift-off)
• spectroscopic ellipsometry, scanning electron microscopy, electrical transport
  
The experiments take place at the Insitut für Halbleitertechnik (IHT). Contact: Dr. Birger Berghoff

 

The e-mail addresses of the tutors can be found by clicking the respective link.

Most student labs are in the Modulbau (MB) next to the physics hall in front of tower 26. The laboratory experiments take place in the Physikzentrum.

Overview: Experiments

Experiments (Solid state physics)

N1	Atomic/Magnetic Force Microscopy (AFM / MFM) (2 days) Room: MB 007, Details / Instructions Download: Instructions Paper Templates Please note that the protocol has the be written as a publication in the APS style (5 to 7 pages long). Download the file "Paper Templates". Open the file "scientificwriting.pdf" and read it carefully before the experiment day. The content of "scientificwriting.pdf" will be part of the discussion prior the experiment.
N3	Superconductivity and SQUID Room: MB 012, Details / Instructions Download: Anleitung
N8	Fabrication and Characterization of Pseudo-MOSFETs (2 days) Room: 24C203, Details / Instructions Download: In recent years, microelectronics has undergone an enormous evolution with a steadily increasing performance and complexity of integrated circuits. This has been made possible by modern CMOS technology and in particular the down-scaling of the structural dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) devices. However, scaling leads to the appearance of so-called short-channel effects (SCEs) that result in excessive leakage current and thus lead to an increased power consumption. Employing silicon-on-insulator (SOI) with ultrathin silicon thickness, SCEs can effectively be suppressed. The manufacturing process of SOI, however, is rather involved and can result in deteriorated carrier transport properties. Therefore, so-called pseudo-MOSFET are fabricated that facilitate a characterization of the electronic transport after a very short fabrication cycle. Using the silicon handle wafer as a large area back-gate allows manufacturing the pseudo-MOSFETs with only two lithography and etching process steps. Within this two-day experiment students will fabricate and characterize pseudo-MOSFETs. The Experiment starts always on Tuesday, the day before the date given the schedule. The 2nd day is the Wednesday, the date of which is given in the schedule.

 

Phone

Our staff can be reached via phone

from inside the RWTH:	use the listed 5-digit direct dial
from Aachen	use a prefix: 80-(direct dial)
from Germany	use a prefix: 0241-80-(direct dial)
from outside Germany	use a prefix: +49-241-80-(direct dial)